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| Micrel, Inc. TRIPLE D FLIP-FLOP SY100S331 SY100S331 FEATURES s s s s s s s s s s s Max. toggle frequency of 800MHz Differential outputs IEE min. of -80mA Industry standard 100K ECL levels Extended supply voltage option: VEE = -4.2V to -5.5V Voltage and temperature compensation for improved noise immunity Internal 75K input pull-down resistors 150% faster than Fairchild 40% lower power than Fairchild Function and pinout compatible with Fairchild F100K Available in 24-pin CERPACK and 28-pin PLCC packages DESCRIPTION The SY100S331 offers three D-type, edge-triggered master/slave flip-flops with true and complement outputs, designed for use in high-performance ECL systems. Each flip-flop is controlled by a common clock (CPc), as well as its own clock pulse (CPn). The resultant clock signal controlling the flip-flop is the logical OR operation of these two clock signals. Data enters the master when both CPc and CPn are LOW and enters the slave on the rising edge of either CPc or CPn (or both). Additional control signals include Master Set (MS) and Master Reset (MR) inputs. Each flip-flop also has its own Direct Set (SDn) and Direct Clear (CDn) signals. The MR, MS, SDn and DCn signals override the clock signals. The inputs on this device have 75K pull-down resistors. BLOCK DIAGRAM CD2 CPC CP2 D2 SD2 CD1 CP1 D1 SD1 CD0 CP0 D0 SD0 CD CP D SD Q2 Q2 PIN NAMES Pin CP0 - CP2 CPc D0 - D2 CD0 - CD2 CD CP D SD Q1 Q1 SDn MR MS Q0 - Q2 Q0 - Q2 CD CP D SD Q0 Q0 VEES VCCA Function Individual Clock Inputs Common Clock Input Data Inputs Individual Direct Clear Inputs Individual Direct Set Inputs Master Reset Input Master Set Input Data Outputs Complementary Data Outputs VEE Substrate VCCO for ECL Outputs MS MR M9999-032206 hbwhelp@micrel.com or (408) 955-1690 Rev.: H Amendment: /0 1 Issue Date: March 2006 Micrel, Inc. SY100S331 PACKAGE/ORDERING INFORMATION SD0 CD0 CP0 VEES Ordering Information 4 3 Q1 Q1 VCCA VCC VCC Q2 Q2 D0 Q0 Q0 11 10 9 8 7 6 MS CPC VEE VEES MR SD1 D1 12 13 14 15 16 17 18 Top View PLCC J28-1 5 Part Number SY100S331FC SY100S331FCTR(1) SY100S331JC SY100S331JCTR(1) SY100S331JZ(2) SY100S331JZTR(1, 2) Notes: Package Type F24-1 F24-1 J28-1 J28-1 J28-1 J28-1 Operating Range Commercial Commercial Commercial Commercial Commercial Commercial Package Marking SY100S331FC SY100S331FC SY100S331JC SY100S331JC SY100S331JZ with Pb-Free bar-line indicator SY100S331JZ with Pb-Free bar-line indicator Lead Finish Sn-Pb Sn-Pb Sn-Pb Sn-Pb Matte-Sn Matte-Sn 2 1 28 27 26 19 20 21 22 23 24 25 CD1 SD2 VEES 28-Pin PLCC (J28-1) SD1 MR VEE CPC MS D1 CD2 CP2 D2 CP1 1. Tape and Reel. 2. Pb-Free package is recommended for new designs. CP1 CD1 SD2 CD2 CP2 D2 1 2 3 4 5 6 24 23 22 21 20 19 18 17 Top View 16 Flatpack 15 F24-1 14 13 7 8 9 10 11 12 SD0 CD0 CP0 D0 Q0 Q0 Q2 Q2 VCC VCCA 24-Pin Cerpack (F24-1) M9999-032206 hbwhelp@micrel.com or (408) 955-1690 Q1 Q1 2 Micrel, Inc. SY100S331 TRUTH TABLES Asynchronous Operation(1) Inputs Dn X X X CPn X X X CPc X X X MS SDn H L H MR DCn L H H Outputs Qn (t+1) H L U Dn L H L H X X X CPn u u L L L H X Synchronous Operation(1) Inputs CPc L L u u L X H MS SDn L L L L L L L MR DCn L L L L L L L Outputs Qn L H L H Qn (t) Qn (t) Qn (t) NOTE: 1. H = High Voltage Level, L = Low Voltage Level, X = Don't Care, U = Undefined, t = Time before CP Positive Transition, t+1 = Time after CP Positive Transition, u = Low-to-High Transition NOTE: 1. H = High Voltage Level, L = Low Voltage Level, X = Don't Care, U = Undefined, t = Time before CP Positive Transition, t+1 = Time after CP Positive Transition, u = Low-to-High Transition DC ELECTRICAL CHARACTERISTICS VEE = -4.2V to -5.5V unless otherwise specified, VCC = VCCA = GND Symbol IIH IEE Parameter Input HIGH Current, All Inputs Power Supply Current Min. -- -80 Typ. -- -65 Max. 200 -35 Unit A mA VIN = VIH (Max.) Inputs Open Condition M9999-032206 hbwhelp@micrel.com or (408) 955-1690 3 Micrel, Inc. SY100S331 AC ELECTRICAL CHARACTERISTICS CERPACK VEE = -4.2V to -5.5V unless otherwise specified, VCC = VCCA = GND TA = 0C Symbol fmax tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tTLH tTHL tS Parameter Toggle Frequency Propagation Delay CPc to Output Propagation Delay CPn to Output Propagation Delay CDn, SDn to Output Propagation Delay MS, MR to Output Transition Time 20% to 80%, 80% to 20% Set-up Time Dn CDn, SDn (Release Time) MS, MR (Release Time) Hold Time Dn Pulse Width HIGH CPn, CPc, DCn SDn, MR, MS Min. 800 300 300 300 300 300 Max. -- 800 800 900 1000 900 TA = +25C Min. 800 300 300 300 300 300 Max. -- 800 800 900 1000 900 TA = +85C Min. 800 300 300 300 300 300 Max. -- 800 800 900 1000 900 Unit MHz ps ps ps ps ps ps 400 500 800 300 800 -- -- -- -- -- 400 500 800 300 800 -- -- -- -- -- 400 500 800 300 800 -- -- -- -- -- ps ps Condition tH tpw (H) PLCC VEE = -4.2V to -5.5V unless otherwise specified, VCC = VCCA = GND TA = 0C Symbol fmax tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tTLH tTHL tS Parameter Toggle Frequency Propagation Delay CPc to Output Propagation Delay CPn to Output Propagation Delay CDn, SDn to Output Propagation Delay MS, MR to Output Transition Time 20% to 80%, 80% to 20% Set-up Time Dn CDn, SDn (Release Time) MS, MR (Release Time) Hold Time Dn Pulse Width HIGH CPn, CPc, DCn SDn, MR, MS Min. 800 300 300 300 300 300 Max. -- 700 700 800 900 900 TA = +25C Min. 800 300 300 300 300 300 Max. -- 700 700 800 900 900 TA = +85C Min. 800 300 300 300 300 300 Max. -- 700 700 800 900 900 Unit MHz ps ps ps ps ps ps 400 500 800 300 800 -- -- -- -- -- 400 500 800 300 800 -- -- -- -- -- 400 500 800 300 800 -- -- -- -- -- ps ps Condition tH tpw (H) M9999-032206 hbwhelp@micrel.com or (408) 955-1690 4 Micrel, Inc. SY100S331 TIMING DIAGRAMS DATA 0.7 0.1 ns 0.7 0.1 ns -0.95V 80% 50% 20% -1.69V CLOCK 1/fmax tPHL tPLH tpw (H) OUTPUT 50% tPLH tPHL OUTPUT tTLH tTHL Propagation Delay (Clock) and Transition Times Note: VEE = -4.2V to -5.5V unless otherwise specified, VCC = VCCA = GND 0.7 0.1 ns SDn, CDn MS, MR 0.7 0.1 ns +1.05V 80% 50% 20% +0.31V tS (RELEASE TIME) tpw (H) CLOCK tPHL OUTPUT tPLH OUTPUT tPLH 50% tPHL 50% 80% 50% 20% Propagation Delay (Sets and Resets) M9999-032206 hbwhelp@micrel.com or (408) 955-1690 5 Micrel, Inc. SY100S331 TIMING DIAGRAMS +1.05V DATA th tS +1.05V CLOCK 50% +0.31V Data Setup and Hold Time Notes: ts is the minimum time before the transition of the clock that information must be present at the data input. th is the minimum time after the transition of the clock that information must remain unchanged at the data input. 50% +0.31V M9999-032206 hbwhelp@micrel.com or (408) 955-1690 6 Micrel, Inc. SY100S331 24-PIN CERPACK (F24-1) Rev. 03 M9999-032206 hbwhelp@micrel.com or (408) 955-1690 7 Micrel, Inc. SY100S331 28-PIN PLCC (J28-1) Rev. 03 MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 TEL USA + 1 (408) 944-0800 FAX + 1 (408) 474-1000 WEB http://www.micrel.com The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. (c) 2006 Micrel, Incorporated. M9999-032206 hbwhelp@micrel.com or (408) 955-1690 8 |
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